1. Field of the Invention
The present invention generally relates to integrated circuits, and more particularly to electroplating copper interconnects.
2. Background of Invention
Advancements in the area of semiconductor fabrication have enabled the manufacturing of integrated circuits that have a high density of electronic components. The length and number of interconnect wiring increases in high density integrated circuits. Three-dimensional (3D) stacking of integrated circuits has been created to address these challenges. Fabrication of 3D integrated circuits includes at least two silicon chips stacked vertically. Vertically stacked chips can reduce interconnect wiring length and increase device density. Deep through-substrate vias (TSVs) can provide interconnections and electrical connectivity between the electronic components of the vertically stacked chips. Such vias may require high aspect ratios, where the via height is large with respect to the via width, to save valuable area on the silicon substrate. TSVs enable increased device density while reducing the total length of interconnect wiring.
However, fabrication techniques such as chemical vapor deposition (CVD) are unable to fill high aspect ratio TSVs without the risk of pinch-off. Pinch-off refers to build up of deposited material at an opening of a trench or a via hole (e.g., TSV). Pinch-off can result in the formation of voids, where some volume of a trench or a via hole (e.g., TSV) remain unfilled with the deposited material. Void formation can reduce the conductive cross section and if large enough may constitute a short and sever the interconnect structure. Thus, void formation can reduce integrated circuit performance, decrease reliability of interconnects, cause sudden data loss, and reduce the useful life of semiconductor integrated circuit products. In addition, pinch-off can result in undesired process chemicals to be trapped within a trench or a via hole (e.g., TSV).
An alternative technique for filling TSVs with conductive material may include electroplating. Electroplating techniques require a cathode. IF the part to be plated is conductive, it can serve as the cathode. The cathode can be connected to a negative terminal of an external power supply and thus must be electrically conductive. A seed layer can be deposited to serve as the cathode. For example, a copper film may be deposited using physical vapor deposition or other known deposition techniques to form the requisite cathode, or seed layer, in preparation for electroplating. When electroplating a trench or via hole an electrical potential is applied to the cathode while the structure is exposed to an electrolyte solution where the desired plating material can plate out onto the cathode. However, in high aspect ratio features, the risk of pinch-off remains because the deposition on sidewalls and bottom can proceed roughly at the same rate, so the feature closes from the sides before fully filling from the bottom (this tendency is exacerbated by mass transfer limitations at the remote end of a deep feature).
Accordingly, current fabrication techniques for filling high aspect ratio TSVs with a conductive material show risks and disadvantages. Despite achievements that have been made in 3D integrated circuit technology, to increase device density and reduce the length of interconnection wiring, the challenge of fabricating and filling high aspect ratio TSVs without void formation and chemical entrapment continues to persist.